1. Field of the Invention
The present invention is directed in general to the field of data processing systems. In one aspect, the present invention relates to dynamic power control in pipelined processor systems.
2. Description of the Related Art
In pipelined processor designs, individual pipeline stages are typically designed to provide maximum performance by minimizing latencies to and from memory and maximizing bandwidths at each stage. However, such processors are often “over-designed” because typical processor usage does not require that all of the stages perform maximally in every clock cycle. Where processors are designed to execute maximally whenever possible, their operation can cause substantial power dissipation and can actually lead to decreased performance for some instruction distributions. For example, when executing a workload having a naturally low instruction-level parallelization (ILP), a processor pipeline need not operate in a full power/high-throughput mode, and indeed, such a mode of operation may negatively impact performance due to higher latencies in the units and cost power unnecessarily. Accordingly, there is a need for a system and method for controlling the performance and power dissipation in a pipelined processor system. In addition, there is a need for a pipelined processor system and design which provides the required level of performance and throughput without excessive power dissipation. Further limitations and disadvantages of conventional solutions will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.